View STV6618_217516.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
STV6618
Video Switch Matrix for DVDs
Main Features
s IC Bus Control s 5 Y/CVBS Inputs, 3 Y/CVBS Outputs s 3 C Inputs, 1 C Output s 2 RGB/YPrPb Inputs, 1 RGB/YPrPb Output s 6 dB Gain on all 150 Buffer Outputs s Integrated 150 Buffers s Video Muting on all Outputs s Bottom Clamp on all CVBS/Y, Average Clamp on C Inputs, Bottom Clamp on RGB, Sync-tip Clamp on PrPb signals s Bandwidth: 17 MHz s Crosstalk: 50 dB
TQFP44 (10 x 10 x 1.4 mm) (Thin Full Plastic Quad Flat Pack)
Description
The STV6618 is a highly integrated IC buscontrolled video switch matrix, optimized for use in recordable Digital Video Disk applications or DVD players. It is adapted to video signals with 1H and 2H formats video routings. It provides required for connections to two external devices (Europe 2 SCARTs), internal tuners, digital encoders and recorders.
ORDER CODE: STV6618
September 2003
1/24
STV6618
Table of Contents
Chapter 1
1.1 1.2
GENERAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Connections .................................................................................................................. 3 Pin Description ................................................................................................................... 4
Chapter 2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Absolute Maximum Ratings ................................................................................................ 7 Thermal Data ...................................................................................................................... 7 Recommended Operating Conditions .................................................................................. 7 Video Section Characteristics .............................................................................................. 8 Fast Blanking Section Characteristics ................................................................................. 9 Chroma Section Characteristics ......................................................................................... 10 Digital Outputs .................................................................................................................... 10 IC Bus Characteristics ...................................................................................................... 11
Chapter 3
3.1 3.2
IC BUS SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IC Bus Addresses ............................................................................................................. 12 Power-on Reset: Bus Register Initial Conditions ............................................................... 15
Chapter 4 Chapter 5 Chapter 6 Chapter 7
INPUT/OUTPUT GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 APPLICATION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PACKAGE MECHANICAL DATA
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2/24
STV6618
GENERAL OVERVIEW
1
1.1
GENERAL OVERVIEW
Pin Connections
Figure 1: Pinout Diagram
33 32 31 30 29 28 27 26 25 24 23
FBOUT_TV FBIN_AUX VDD SCL SDA GNDD CIN_TV Y/CVBSIN_TV DIGOUT1 CIN_TUN DIGOUT2
34 35 36 37 38 39 40 41 42 43 44
Y/CVBSOUT_TV VCCB3 R/PR/COUT_TV VCCB2 G/YOUT_TV C_GATE B/PBOUT_TV GNDB Y/CVBSOUT_AUX VCCB 1 COUT_AUX
22 21 20 19 18 17 16 15 14 13 12
GNDB_REC Y/CVBSOUT_REC VCCB_REC Y/CVBSIN_AUX DIGOUT6 R/PR/CIN_AUX DIGOUT5 G/YIN_AUX DIGOUT4 B/PBIN_AUX GND2
1 2 3 4 5 6 7 8 9 10 11 Y/CVBSIN_TUN DIGOUT3 GND1 CVBSIN_ENC DECV CIN_ENC YIN_ENC VCC R/PR/CIN_ENC G/YIN_ENC B/PBIN_ENC
3/24
GENERAL OVERVIEW
STV6618
1.2
Pin Description
Symbol
Y/CVBSIN_TUN DIGOUT3 GND1 CVBSIN_ENC DECV CIN_ENC YIN_ENC VCC R/PR/CIN_ENC G/YIN_ENC B/PBIN_ENC GND2 B/PBIN_AUX DIGOUT4 G/YIN_AUX DIGOUT5 R/PR/CIN_AUX DIGOUT6 Y/CVBSIN_AUX VCCB_REC Y/CVBSOUT_REC GNDB_REC COUT_AUX VCCB1 Y/CVBSOUT_AUX GNDB B/PBOUT_TV C_GATE G/YOUT_TV VCCB2 R/PR/COUT_TV VCCB3 Y/CVBSOUT_TV FBOUT_TV FBIN_AUX Y/CVBS Input from Tuner Digital Output Pin 3 Ground Supply 1 for Video Inputs CVBS Input from Encoder Video decoupling capacitor Chroma Input from Encoder Y Input from Encoder +5 V Power Supply for Video Inputs Red or Pr or Chroma Input from Encoder Green or Y Input from Encoder Blue or Pb Input from Encoder Ground Supply 2 for Video Inputs Blue or Pb Input from Auxiliary (SCART2 or external Cinch) Digital Output Pin 4 Green or Y Input from Auxiliary (SCART2 or external Cinch) Digital Output Pin 5 Red or Pr or Chroma input from Auxiliary (SCART2 or external Cinch) Digital Output Pin 6 Y/CVBS Input from Auxiliary (SCART2 or external Cinch) Video Output Recorder Buffer Supply Pin Y/CVBS Output to Recorder Ground Supply for Recorder Buffer Chroma Output to Auxiliary (SCART2 or external Cinch) Video Output Buffer Supply Pin Y/CVBS Output to Auxiliary (SCART2 or external Cinch) Ground Supply for Video Buffer Blue or Pb Output to TV (SCART1 or external Cinch) External Transistor Command for Bidirectinnal B/C SCART I/O Green or Y Output to TV (SCART1 or external Cinch) Video Buffer Red or Pr or Chroma Output to TV (SCART1 or external Cinch) Video Output Buffer Supply Pin Y/CVBS Output to TV (SCART1 or external Cinch) Fast Blanking Output to TV (SCART1) Fast Blanking Input from Auxiliary (SCART2)
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Description
4/24
STV6618
Pin No.
36 37 38 39 40 41 42 43 44
GENERAL OVERVIEW
Symbol
VDD SCL SDA GNDD CIN_TV Y/CVBSIN_TV DIGOUT1 CIN_TUN DIGOUT2 +5 V Digital Power Supply IC Bus Clock IC Bus Data Digital Ground Supply Chroma Input from TV (SCART1 or external Cinch) Y/CVBS Input from TV (SCART1 or external Cinch) Digital Output Pin 1 Chroma Input from Tuner Digital Output Pin 2
Description
Figure 2: STV6618 Input/Output Diagram
R/PR/CIN_ENC G/YIN_ENC B/PBIN_ENC
R/PR/COUT_TV G/YOUT_TV B/PBOUT_TV FBOUT_TV Y/CVBSOUT_TV CIN_TV Y/CVBSIN_TV
Encoder
CVBSIN_ENC CIN_ENC YIN_ENC
SCART1 TV
Y/CVBSIN_TUN Y/CVBS_REC
Tuner
Recorder
STV6618
(TQFP 44)
CIN_TUN
COUT_REC
C_GATE DIGOUT1 DIGOUT2
Transistor
COUT_AUX
DIGOUT3 DIGOUT4 DIGOUT5
SCART2 (Auxiliary)
Y/CVBSOUT_AUX
R/PR/CIN_AUX G/YIN_AUX B/PB_AUX FBIN_AUX Y/CVBSIN_AUX
DIGOUT6
5/24
6/24
B/PbIN_ENC R/Pr/CIN_ENC G/YIN_ENC B/PbIN_AUX R/Pr/CIN_AUX G/YIN_AUX CIN_ENC CIN_TV CIN_TUN YIN_ENC CVBSIN_ENC Y/CVBS_AUX Y/CVBS_TV Y/CVBS_TUN CVBSIN_TUN Y/CVBSIN_TV Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC 0 dB mute
STV6618
Y/CVBSIN_TUN
Bo. Clamp
Y/CVBSOUT_REC Recorder
Y/CVBSIN_TV
Bo. Clamp
GENERAL OVERVIEW
Y/CVBSIN_AUX
Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC 6 dB mute
Bo. Clamp
CVBSIN_ENC
Bo. Clamp
YIN_ENC
6 dB
Bo. Clamp
Y/CVBSOUT_TV SCART1
CIN_TUN
mute
Av. Clamp
CVBSIN_TUN Y/CVBSIN_TV CVBSIN_ENC YIN_ENC
CIN_TV
CIN__TUN CIN__TV CIN_ENC 6 dB mute
Av. Clamp
Y/CVBSOUT_AUX SCART2
CIN_ENC
Av. Clamp
COUT_AUX
G/YIN_AUX
Bo. Clamp Sync Sep.
R/PR/CIN_AUX
Bot/Sync/Av. Bo. / Sync
mute G/YIN_AUX G/YIN_ENC mute CIN_ENC R/Pr/CIN_AUX R/Pr/CIN_ENC
6 dB
B/PBIN_AUX
R/Pr/COUT_TV SCART1
6 dB
Figure 3: STV6618 Block Diagram
G/YIN_ENC
Bo. Clamp Sync Sep.
G/YOUT_TV SCART1
R/PR/CIN_ENC
Bot/Sync/Av. Bo. / Sync
B/PbIN_AUX B/PbIN_ENC mute 6 dB
B/PBIN_ENC
B/PbOUT_TV SCART1
FBIN_AUX 5v 0v
FBIN_AUX
SCL
FBOUT_TV
SDA
IC Bus
DIGOUT2
DIGOUT3
STV6618
C_GATE
DIGOUT4
DIGOUT5
DIGOUT6
DIGOUT1
STV6618
ELECTRICAL CHARACTERISTICS
2
2.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Digital Section Video Section Voltage at Pin 1 to GND - Video pins - Bus pins, DIGOUT1,2,3 and C_GATE Voltage at pin DIGOUT4-5-6 Maximum ESD voltage allowed. 100 pF capacitor discharged through 1.5 k serial resistor (Human Body Model) Operating Ambient Temperature Storage Temperature
Symbol
VDD VCCV VI VDIGOUT4-5-6 VESD TOPER TSTG
Value
6 6
Unit
V V
0, 5.5 0, 5.5 0, 13 4 0, +70 -20, +150
V
V kV C C
2.2
Thermal Data
Parameter
Junction-ambient Thermal Resistance (Maximum) on a single-layer board
Symbol
RthJA
Value
70
Unit
C/W
2.3
Recommended Operating Conditions
TAMB = 25 C, VCCV = 5 V, VDD = 5 V, ROUT_VREC = 4.7 k, ROUT_VBUF = 150 , unless otherwise specified. Output impedances of sources: RGV = 75 .
Symbol
Supply Voltages VDD VCCV
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Digital Supply Voltage Video Operating Supply Voltage
4.75 4.75
5.00 5.00
5.25 5.25
V V
Active Mode (All channels ON) IDD ICCV Digital Supply Current Total Video Supply Current VDD = 5 V, VCCV = 5 V, No Load 3.5 31 5.0 45 6.5 58 mA mA
Standby Mode (All channels OFF) IDD ICCVSTD Digital Supply Current Total Video Supply Current VDD = 5 V VCC = 5 V 3.0 4.5 0.5 6.0 1.0 mA mA
7/24
ELECTRICAL CHARACTERISTICS
STV6618
2.4
Video Section Characteristics
TAMB = 25 C, VCCV = 5 V, VDD = 5 V, ROUT_VREC = 4.7 k, ROUT_VBUF = 150 , unless otherwise specified. Output impedances of sources: RGV = 75 .
Symbol
VDCIN_BOT ICLAMP_BOT ILEAK VDCIN_YSYNC VDCIN_SYNC ICLAMP_SYNC CIN VIN DYN
Parameter
DC Input Level Clamping Current, Bottom clamp Input Leakage Current DC Input Level DC Input Level Max. Clamping Current during Sync Clamp Input Capacitance Maximum Input Signal Dynamic Output Signal Bandwidth at -3 dB Y/CVBS OUT RGB OUT Pr/Pb OUT Video Band Gain Spread (15 kHz to 5 MHz) Y/CVBS OUT RGB OUT Pr/Pb OUT Crosstalk Isolation between Input Channel Crosstalk Isolation between Output Channel Output Resistance
Test Conditions
Bottom Sync Pulse at VDCIN - 400 mV VIN = VDCIN + 1 V, Bottom clamp input Y input, YPrPb mode, Black Level Sync clamp input (Pr,Pb) Sync signal on Y input Sync clamp input (Pr,Pb) at VDCIN - 400 mV
Min.
1.9 1
Typ.
2.0 2 1
Max.
2.2 3 5 2.5 3.1
Unit
V mA A V V
2.2 2.9
2.3 3.0
100 2
A pF 1.5 1.0 3 2 VPP VPP
Y/CVBS, RGB Pr, Pb Y/CVBS, RGB Pr, Pb VIN = 0.7 VIN = 0.7 VIN = 0.7 VPP VPP VPP
BW
14 14 14
17 17 17
MHz
Flatness
VIN = 1 VIN = 1 VIN = 0.7
VPP VPP VPP 541 501 60
0.5 0.5 0.5
dB
CTi
VIN = 1 VPP at 4.43 MHz on 1 point VIN = 1 VPP at 4.43 MHz on 1 point, RLOAD = 150
dB
CTo ROUT G0V
55 5 10 0.5
dB
dB
Gain at video outputs (0 dB), recorder VIN = 1 VPP and Gain = 0 dB at output 1 MHz Gain at video outputs (6 dB) VIN = 1 VPP and Gain = 6 dB at 1 MHz VIN = 0.7 VPP and Gain = 6 dB at 1 MHz Bottom Sync Pulse2 Mute
2
-0.5
0.0
G6V
5.5
6.0
6.5
dB
RGBmatch
Gain matching Between RGB outputs DC Output Voltage, TV and AUX Y/CVBS outputs DC Output Voltage, Recorder Y/CVBS Output
-0.3 0.32 0.57 1.2 1.3 0.40 0.60 1.3 1.4
0.3 0.43 0.67 1.4 1.5
dB
DCOUTZY/CVSS
V
DC OUTREC
Bottom Sync Pulse2 Mute2
V
8/24
STV6618
Symbol
DCOUTRGB
ELECTRICAL CHARACTERISTICS
Parameter
DC Output Voltage, RGB outputs
Test Conditions
Black Level2 Mute
2
Min.
0.45 0.50 0.50 0.45 1.4 1.4
Typ.
0.60 0.60 0.60 0.60 1.5 1.5 0.2 0.3
Max.
0.70 0.70 0.70 0.70 1.6 1.6 2.5 5
Unit
V
DC OUTYOUT
DC Output Voltage, TV Y Output (G/ YOUT_TV, YPrPb mode)
Bottom Sync Pulse2 Mute2 Black Level2 Mute2 VIN = 1 VPP at 4.43 MHz VIN = 1 VPP at 4.43 MHz VIN = 1 VPP at 5 MHz on 1 point
V
DCOUTPrPb DPHI DG Mute LNL VSN
DC Output Voltage, PrPb outputs Differential Phase, Y/CVBS Differential Gain, Y/CVBS Mute Suppression Luminance non-linearity Video Signal-to-Noise Ratio3
V deg. % dB
-55 0.3 75 3
% dB
1. Minimum Crosstalk values estimated during Qualification phase, based on ST Evaluation Board measurement, TQFP44 package soldered on board. 2. Measured at IC output pin. 3. Signal-to-Noise = 20log (VOUTblack-to-white = 0.7 VPP / Vnoise(mVrms) weighted CCIR 567)
2.5
Fast Blanking Section Characteristics
Parameter Test Conditions Min. Typ. Max. Unit
Symbol
INPUT MODE FBLOW/HIGH IIN OUTPUT MODE FBLOW FBHIGH
Input Low/High Level Threshold Input Current
0.4
0.7 2
0.9 10
V A
Output Low Level Output High Level
RLOAD = 150 RLOAD = 150 At 50% on digital RGB transients, at 2 V on FB rise transient, at 1 V on FB fall, CLOAD = 10 pF maximum CLOAD = 10 pF maximum between 10% and 90% between 90% and 10% 3.0 3.4
0.5 3.8
V V
FBDEL
Fast Blanking RGB delay
15
ns
FBTRANS
FB Transitions at FB output Rise Time Fall Time
10 10
ns
9/24
ELECTRICAL CHARACTERISTICS
STV6618
2.6
Chroma Section Characteristics
TAMB = 25 C, VCCV = 5 V, VDD = 5 V, ROUT_VREC = 4.7 k, ROUT_VBUF = 150 , unless otherwise specified. Output impedances of sources: RGV = 75 .
Symbol
VDCIN RIN CIN VIN DYN DC OUT CBW CTi
Parameter
DC Input Level Input Resistance Input Capacitance Max Input Signal Dynamic Output Signal DC Output Voltage AUX C Output Chroma Bandwidth Crosstalk Isolation between Input Channel Crosstalk Isolation between Output Channel Output Resistance Gain at Chroma Outputs Mute Suppression Chroma to Luma Delay, Source Y/C
Test Conditions
Min.
2.9 30
Typ.
3.0 50 2
Max.
3.1
Unit
V k pF
1.0 2.0 No Chroma input signal1 VIN = 1 VPP at -3 dB VIN = 1 VPP at 4.43 MHz, on one input VIN = 1 VPP at 4.43 MHz, on one input, RLOAD = 150 1.4 10 542 50 2 1.5 15 60 1.6
VPP VPP V MHz dB
CTo ROUT G6C Mute CToYdel
55 5 10 6.5
dB dB dB 20 ns
VIN = 1 Vpp and Gain = 6 dB at 1 MHz VIN = 1 VPP at 4.43 MHz, on one input VIN = VPP at 4.43 MHz
5.5 -55
6.0
1. Measured at IC output pin. 2. Minimum Crosstalk values estimated during Qualification phase, based on ST Evaluation Board measurement, TQFP44 package soldered on board.
2.7
Digital Outputs
TAMB = 25 C, VCCV = 5 V, VDD = 5 V.
Symbol
C_gate_H C_gate_L C_gate_H
Parameter
Pull-up resistor value to VccB3 Output Low level Output High level External pull-up resistor value to VDD Output low level, DIGOUT1-2-3
Test Conditions
Min.
16
Typ.
20
Max.
24 0.3 0.7 VDD
Unit
k V V k
IIN = 0 mA IIN = 1 mA RLOAD = 20 k 10 RLOAD = 10 k RLOAD = 10 k RLOAD = 10 k, Opened collector output ILOAD = 2 mA Opened Collector Output 2.2
DIGOUT1-2-3 Load DIGOUT1-2-3 Low
0.7
V V
DIGOUT1-2-3 Middle Output middle level, DIGOUT1-2-3 DIGOUT1-2-3 High DIGOUT4-5-6 Low DIGOUT4-5-6 High Output high level,DIGOUT1-2-3 Output low level, DIGOUT4-5-6 Output high level, DIGOUT4-5-6
VDD 0.7 13
V V V
10/24
STV6618
ELECTRICAL CHARACTERISTICS
2.8
IC Bus Characteristics
TAMB = 25 C, VCCV = 5 V, VDD = 5 V
Symbol
SCL VIL VIH ILI SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Low Level Input Voltage High Level Input Voltage Input Leakage Current VIN = 0 to 5.5 V
-0.3 2.3 -10 0
1.5 5.5 10
V V s
Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance 1.5 V to 3 V 3 V to 1.5 V IOL = 3 mA 3 V to 1.5 V VIN = 0 to 5.5 V
-0.3 2.3 -10 0
1.5 5.5 10 10 1 300 0.4 250 400
V V s pF s ns V ns pF
Clock Low Period Clock High Period Data Setup Time Data Hold Time Setup Time from Clock High to Stop Start Setup Time following a Stop Start Hold Time Start Setup Time following Clock Low to High Transition
4.7 4 250 0 4 4.7 4 4.7 340
s s ns ns s s s s
Note:
The device can also operate at 400 kHz and can interface with +3.3 V or + 5 V logic levels.
Figure 4: IC Bus Timing
SDA
t BUF t LOW tSU,DAT
SCL tHD,STA tR t HD,DAT t HIGH tF tSU,STO
SDA
tSU,STA
11/24
IC BUS SELECTION
STV6618
3
IC BUS SELECTION
Data transfers follow the usual IC format; i.e. after the start condition (S), a 7-bit slave address is sent, followed by an eight-bit data direction bit (W). An 8-bit sub-address is sent to select a register, followed by an 8-bit data word to be included in the register. The IC's IC bus decoder enables the automatic incrementation mode in write mode. String Format Write only mode (S = Start condition, P = Stop condition, A = Acknowledge)
S Slave Address 0 A Sub-address A Data A P
Read only mode
S Slave Address 1 A Data A P
Slave Address
Address Value A7 1 A6 0 A5 0 A4 1 A3 0 A2 1 A1 0
Auto Increment Mode
S Slave Address 0 A Sub-address A DATA0 A DATA1 A .... DATAn A P
Sub-Address
Sub-Address +1 Sub-Address + N
3.1
IC Bus Addresses
Write Address: 1001 0100 = 94(hex) Input Signal Summary (Write Mode)
Reg Addr (Hex)
Data d7 d6 d5 d4 d3 d2 d1 d0
Y/CVBS and C Output Selection 00 01 DigOUT6 DigOUT5 Not Used Not Used TV Y/CVBS Output Selection Auxiliary C Output Selection Recorder Y/CVBS Output Selection Auxiliary Y/CVBS Output Selection
RGB/YPrPb & Fast Blanking Selection 02 RGB/YPrPb High Impedance State RGB or YPrPb or C mode Selection Auxiliary or Encoder Selection Fast Blanking Selection
Digital Outputs 03 DIGOUT4 DIGOUT3 DIGOUT2 Control DIGOUT1 Control C_GATE Control
12/24
STV6618
Reg Addr (Hex)
Standby 04 TV Output Standby AUX Chroma AUX CVBS Output Output Standby Standby REC Output Standby AUX Input Disable TV Input Disable
IC BUS SELECTION
Data d7 d6 d5 d4 d3 d2 d1 d0
TUN Input Disable
ENC Input Disable
Note:
Unused data must be set to "0".
Reg. Addr (Hex)
Data Description Bits d7
X X X X X X X X X X X X 0 1 X X X X X X X X X X X X 0 1
Comments d6
X X X X X X X X X X X X X X X X X X X X X X X X X X X X
d5
X X X X X X X X X X X X X X X X X X X X X X X X X X X X
d4
X X X X X X X X 0 0 1 1 X X X X X X X X X X 0 0 1 1 X X
d3
X X X X X X X X 0 1 0 1 X X X X X X X X X X 0 1 0 1 X X
d2
0 0 0 0 1 1 1 1 X X X X X X 0 0 0 0 1 1 1 1 X X X X X X
d1
0 0 1 1 0 0 1 1 X X X X X X 0 0 1 1 0 0 1 1 X X X X X X
d0
0 1 0 1 0 1 0 1 X X X X X X 0 1 0 1 0 1 0 1 X X X X X X Mute YIN_ENC CVBSIN_ENC Y/CVBSIN_AUX Y/CVBSIN_TV YCVBSIN_TUN Not allowed Not allowed Y/CVBS_AUX YIN_ENC CVBSIN_ENC Mute 0 = Low Level 1 = High Level Y/CVBSin_TV YIN_ENC CVBSIN_ENC YCVBSIN_TUN Mute Not allowed Not allowed Not allowed Mute CIN_ENC CIN_TV CIN_TUN 0 = Low Level 1 = High Level
Recorder Y/CVBS Output Selection
3
00 TV Y/CVBS Output Selection
2
DigOUT6 Control
1
AUX (SCART2) Y/CVBS Output Selection
3
01 AUX (SCART2) Chroma Output Selection
2
DigOUT5 Control
1
13/24
IC BUS SELECTION
Reg. Addr (Hex) Data Description Bits d7
X X X X X X X X X
STV6618
Comments d6
X X X X X X X X X
d5
X X X X X X X X 0
d4
X X X X X X X X 0
d3
X X X X 0 0 1 1 0
d2
X X X X 0 1 0 1 0
d1
0 0 1 1 X X X X X
d0
0 1 0 1 X X X X X FBIN_AUX FB forced to Low Level FB forced to High Level Not allowed RGB/YPrPb_AUX RGB/YPrPb_ENC CIN_ENC (pin 6) at R/Pr/COUT_TV, B/PbOUT & G/YOUT muted RGB/YPrPb mute RGB mode selection, bottom clamp at RGB inputs, AUX. input selected RGB mode selection, bottom clamp at RGB inputs, ENC. input selected CIN_AUX (pin 17)selected, average clamp at R/Pr/CIN_AUX input, GIN_AUX (bottom clamp) selected, BIN_AUX (bottom clamp) selected CIN_ENC (pin 9)selected, average clamp at R/Pr/CIN_ENC input, GIN_ENC (bottom clamp) selected, BIN_ENC (bottom clamp) selected YPrPb mode selection, sync pulse clamp at Pr Pb inputs, black clamp at Y input, AUX. input selected YPrPb mode selection, sync pulse clamp at Pr Pb inputs, black clamp at Y input, ENC. input selected YPrPb mode selection, delayed sync pulse clamp at Pr Pb inputs, black clamp at Y input, AUX. input select YPrPb mode selection, delayed sync pulse clamp at Pr Pb inputs, black clamp at Y input, ENC. input select RGB/YPrPb outputs active RGB/YPrPb outputs high imp state Red output active, Green and Blue high imp. state
Fast Blanking Output Control
2
RGB/YPrPb Output Selection
2
X
X
0
0
0
1
X
X
X
X
0
1
0
0
X
X
X 02
X
0
1
0
1
X
X
RGB or YPrPb or C Selection
2 X X 1 0 0 0 X X
X
X
1
0
0
1
X
X
X
X
1
1
0
0
X
X
X
X
1
1
0
1
X
X
RGB/YPrPb Control
2
0 0 1
0 1 X
X X X
X X X
X X X
X X X
X X X
X X X
14/24
STV6618
Reg. Addr (Hex) Data Description Bits d7
C_Gate Output Control 1 X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X 0 1 1
IC BUS SELECTION
Comments d6
X X X X X X X X 0 1 1 X X X X X X X X X X X X X X 0 1 X X 1
d5
X X X X X X X X X 0 1 X X X X X X X X X X X X 0 1 X X X X 1
d4
X X X X X 0 1 1 X X X X X X X X X X X X X 0 1 X X X X X X 1
d3
X X X X X X 0 1 X X X X X X X X X X X 0 1 X X X X X X X X 1
d2
X X 0 1 1 X X X X X X X X X X X X 0 1 X X X X X X X X X X 1
d1
X X X 0 1 X X X X X X X X X X 0 1 X X X X X X X X X X X X 1
d0
0 1 X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X 1 Low Level High Level Low Level Mid Level High Level Low Level Mid Level High Level Low Level Mid Level High Level 0 = Low Level 1 = High Level Inputs Active Inputs Disabled Inputs Active Inputs Disabled Inputs Active Inputs Disabled Inputs Active Inputs Disabled Y/CVBSOUT_REC Outputs ON Y/CVBSOUT_REC Outputs OFF Y/CVBSOUT_AUX Outputs ON Y/CVBSOUT_AUX Outputs OFF COUT_AUX Outputs ON COUT_AUX Outputs OFF (high imped.) TV Video Outputs ON TV Video Outputs OFF Only IC bus supplied, and digital outputs
DIGOUT1
2
03
DIGOUT2
2
DIGOUT3
2
DIGOUT4 Control ENC Inputs TUN Inputs TV Inputs AUX Inputs 04 REC Outputs AUX Outputs COUT_AUX Output TV Outputs Full Stop
1 1 1 1 1 1 1 1 1 8
3.2
Power-on Reset: Bus Register Initial Conditions
Power-on Reset is active when supply VDD < 3.5 V. Non-significant bits (X) are pre-set to "0".
Reg. Addr (Hex)
00 01 02 03 04
Data Comments d7
0 0 0 0 0
d6
0 0 0 0 0
d5
0 0 0 0 0
d4
0 0 0 0 0
d3
0 0 0 0 0
d2
0 0 0 0 0
d1
0 0 0 0 0
d0
0 0 0 0 0 Rec. CVBS output muted, TV CVBS output to Aux. CVBS input, Digital output low level Aux. CVBS output to TV CVBS input, Aux. Chroma output muted, Digital output low level FB output to Aux. FB input, TV RGB output to Aux. RGB inputs, RGB outputs active C_gate output low level, DIGOUT outputs low level All inputs outputs active
15/24
INPUT/OUTPUT GROUPS
STV6618
4
INPUT/OUTPUT GROUPS
Figure 5: C_Gate Logic Output (Pin 28)
Figure 8: Fast Blanking Inputs (Pin 35)
V DD 5 V
V DD 5 V
VCCB3
VDD 5 V
18 k
50
tri
Protected Pad
Protected Pad
Figure 6: Video Outputs (Pins 23, 25, 27, 29, 31 and 33)
Figure 9: IC Bus SCL I/O (Pin 37)
VCCB1,2,3
VCCB1,2,3
V CCB1,2,3
VDD5 V
VDD_FLOAT
10 k ib
Protected Pad
Protected Pad
Figure 7: YCVBSOUT_REC Recorder Output (Pin 21)
Figure 10: Fast Blanking Output (Pin 34)
V CCB_REC 5 V
V CCB_REC 5 V
VDD
V CCB3 VCCB3
Protected Pad
Protected Pad
16/24
STV6618
INPUT/OUTPUT GROUPS
Figure 11: Bottom Clamped Video Inputs (Pins 1, 4, 7, 19 and 41)
Figure 14: Average Clamped Video Inputs (Pins 6, 40 and 43)
VCC 5 V 2V + VBE
VCC 5 V
VCC 5 V
VCC 5 V
5 k 5 k
15 k
25 k
tri Protected Pad Protected Pad
tri
25 k
Figure 12: DIGOUT 1, 2 and 3 (Pins 42, 44 and 2)
Figure 15: DECV (Pin 5)
VDD 5 V
Float_Bus
VCC 5 V
VCC 5 V
10 k
40 k
Protected Pad
Figure 13: DIGOUT 4, 5 and 6 (Pins 14, 16 and 18)
Figure 16: IC Bus SDA I/O (Pin 38)
V DD 5 V
Float_DigOUT
VDD5 V
VDD_FLOAT
Acknowledge 10 k
Protected Pad
17/24
INPUT/OUTPUT GROUPS
STV6618
Figure 17: R/Pr/C Inputs (Pins 9 and 17)
VCC 5 V V CC 5 V Botclamp
5 k
50 k
Protected Pad
Figure 18: G/Y Inputs (Pins 10 and 15)
VCC 5 V VCC 5 V Botclamp 2V + VBE
sepsel 5 k 15 k tri Protected Pad 20 k
Figure 19: B/Pb Inputs (Pins 11 and 13)
VCC 5 V V CC 5 V Botclamp 2V + VBE
5 k 15 k tri Protected Pad
18/24
STV6618
Figure 20: Power Supply Connection
INPUT/OUTPUT GROUPS
VCCB3 VCCB2
VCCB1 VCCB_REC
Float_VidOUTs
VCC
VDD
Float_VDD
Float_DigOUTs
32
30
24
20
5V
8
5V
36
5V
12 V
26
22
3 GND1
12
39
GNDB GNDB_REC
GND2 GNDD
These symbols represent some huge diode and Zener-like components used for ESD protection of the device. They are not supposed to be paths for any current in normal operation mode.
19/24
APPLICATION DIAGRAMS
STV6618
5
APPLICATION DIAGRAMS
Figure 21: YPrPb Application
TV INPUTS J1 Y/CVBS J2 C C . . J3 Y/CVBS Y
TV OUTPUTS J4 Pr J5 Y J6 Pb
AUX OUTPUTS J7 Y/CVBS J8 C J9 Y/CVBS
AUX INPUTS J10 Pr J11 Y J12 Pb
S-VHS
VCCB R30 75 R31 75 R32 75 R33 75 R34 75 R35 75 R36 75 T2 NPN R37 75 R38 75 R39 75 R40 75 R41 75
R42 470 VCCB C28 33 32 31 30 29 28 27 26 25 24 23 U3 10 R44 75 C25 100n C26 100n C27 100n R43 75 REC C REC Y/CVBS C29 100n
C_GATE
B/Pb_OUT_TV
R/Pr/COUT_TV
Y/CVBSOUT_TV
G/YOUT_TV
34 35 VDD C32 36 SCL C31 37 10 SDA C34 C35 Tuner C C37 100n Tuner Y/CVBS C39 100n 100n 100n 100n 38 39 40 41 42 43 44
Y/CVBSOUT_AUX
COUT_AUX
VCCB3
VCCB2
GNDB
VCCB1
FBOUT_TV FBIN_AUX VDD SCL SDA GNDD CIN_TV Y/CVBSIN_TV DigOUT1 CIN_TUN
GNDB_REC Y/CVBSOUT_REC VCCB_REC Y/CVBSIN_AUX DigOUT6
22 21 20 19 18 C33 17 100n 16 C36 15 1 14 C38 13 100n 12 DOut 4 DOut 5 DOut 6 C30 100n VCCB R45 10K R46 10K 12V R47 10K
STV6618
R/Pr/CIN_AUX DigOUT5 G/YIN_AUX DigOUT4 B/PbIN_AUX
Y/CVBSIN_TUN
R/Pr/CIN_ENC
DigOUT2
GND2 B/PbIN_ENC 11 G/YIN_ENC 10
CVBSIN_ENC
CIN8ENC
YIN8ENC 7
DigOUT3
GND1
DECV
1
2
3
4
5
6
8
VCC
9
VCC VCC R48 R49 R50 C43 100n 10K 10K 10K DOut 1 DOut 2 DOut 3 C44 C45 100n100n C46 1 100n C48 100n 100n 10 C40 47n C47 C41 C42
R51 R52 R53 R54 R55 R56 R30 to R35: expected loads on Decoder outputs
All grounds must be linked un der the IC ENC Pr ENC C ENC Y ENC CVBS ENC Y ENC Pb
20/24
STV6618
Figure 22: 2 SCART / RGB Signal Application
APPLICATION DIAGRAMS
TV1 SCART
AUX1 SCART
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
R1 75
R2 75
R3 75
R4 75 Q1 JFET N
R5 75
R10 75
R11 75
R12 75
Q2 JFET N
VCCB C4 33
C1 100n
C2 100n
C3 100n
32
31
30
29
28
27
26
25
24
23
U1 10
VCCB3
VCCB2
GNDB
C_GATE
VCCB1
G/YOUT_TV
B/Pb_OUT_TV
Y/CVBSOUT_AUX
Y/CVBSOUT_TV
R/Pr/COUT_TV
COUT_AUX
34 35 VDD C8 SCL C7 37 10 SDA C10 C11 Tuner C C13 100n Tuner Y/CVBS C15 100n 100n 100n 100n 38 39 40 41 42 43 44 36
FBOUT_TV FBIN_AUX VDD SCL SDA GNDD CIN_TV Y/CVBSIN_TV DigOUT1 CIN_TUN
GNDB_REC Y/CVBSOUT_REC VCCB_REC Y/CVBSIN_AUX DigOUT6
22 21 20 19 18 C9 17 100n 16 C12 15 100n 14 C14 13 100n 12 DOut 4 DOut 5 DOut 6 C6 100n VCCB R18 10K R19 10K 12V R20 10K
STV6618
R/Pr/CIN_AUX DigOUT5 G/YIN_AUX DigOUT4 B/PbIN_AUX
Y/CVBSIN_TUN
R/Pr/CIN_ENC
DigOUT2
GND2 B/PbIN_ENC G/YIN_ENC
CVBSIN_ENC
CIN8ENC
YIN8ENC
DigOUT3
DECV
GND1
VCC
10
11
1
2
3
4
5
6
7
8
9
VCC VCC R21 R22 R23 C19 100n 10K 10K 10K DOut 1 DOut 2 DOut 3 C20 C21 100n100n C22 C23 C24 100n100n100n 100n 10 C16 47n C17 C18
R24 R25 R26 R27 R28 R29 R13 to R18: expected loads on Decoder outputs
ENC CVBS
ENC G
ENC C
ENC R
ENC Y
All grounds must be linked un der the IC
ENC B
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R9 75 R6 75 R7 75 R8 75 REC Y/CVBS C5 100n R17 4K7
21/24
PACKAGE MECHANICAL DATA
STV6618
6
PACKAGE MECHANICAL DATA
Figure 23: 44-Pin Thin Quad Flat Package
0.10m m .004 seating plane
A A1 A2 b c D D1 D3 E
b
1.60 0.05 1.35 0.30 0.09 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0 0.45 3.5 0.60 1.00 44 7 0.75 1.40 0.37 0.15 1.45 0.45 0.20 0.002
0.063 0.006 0.053 0.055 0.057 0.012 0.015 0.018 0.004 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.018 0.024 0.030 0.039 0.008
E1 E3 e K L L1
c
Number of Pins N
L1
L
K
22/24
STV6618
REVISION HISTORY
7
REVISION HISTORY
The following table summarizes the modifications applied to this document.
Revision
1.0 First Issue
Description
Date
24 April 2001 27 April 2001
New pinout proposal, to improve connection to TV SCART. Slight correction of electrical parameters (changed value in Bold). Correction of DigOUT1-2-3 IC control specification (changed value in bold) New pinout proposal, To improve connection to SCARTs. Application layout hypothesis: 1 layer PCB, IC on lower side (copper side), SCART on upper side Application diagrams added. VDCin chroma section: 3.0V instead of 2.3V previously. VDCin , video section, PrPb: 3.0V instead of 2.3V previously Add Fast Blanking Section Electrical Characteristics. Update Application Schematic Diagrams 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Addition of Section 4: INPUT/OUTPUT GROUPS on page 16. Document reformatted. Replaced Figure 22: 2 SCART / RGB Signal Application on page 21. CIN = 1 VPP changed to "VIN = 1 VPP in CBW Parameter in Section 2.6. Symbols for a PNP, NPN and current source as well as their connections added to Figure 17. Update of Crosstalk and DC Output voltage data in Section 2.4 and Section 2.6. Modification of Register 2 data in Section 3.1. Replaced Figure 21 and Figure 22. Update of Crosstalk data and Output Voltage values in Section 2.4 and Section 2.6. Updated Figure 3 and Figure 22. Chroma Output Gain (G6C) parameters updated in Section 2.6. Addition of minimum/maximum values for certain parameters in Section 2: ELECTRICAL CHARACTERISTICS. Document upgraded to Datasheet status. Modification of Bandwidth parameter (17 MHz) and Figure 3.
7 May 2001 11 May 2001 7 June 2001 21 June 2001 6 July 2001 2 Oct 2001 10 Oct 2001 26 Oct 2001 14 Jan 2002 24 May 2002 24 Sept. 2002
23/24
REVISION HISTORY
STV6618
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
24/24

▲Up To Search▲

Price & Availability of STV6618

	To Download STV6618 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .